

Verylargescale integration device for parallel vertical group computing the sum of squared differences
Назва  Verylargescale integration device for parallel vertical group computing the sum of squared differences 
Назва англійською  Verylargescale integration device for parallel vertical group computing the sum of squared differences 
Автори  Ivan Tsmots, Ihor. Ihnatiev, Stepan Ivasiev 
Принадлежність  Lviv Polytechnic National University, Lviv, Ukraine,
West Ukrainian National University, Ternopil, Ukraine 
Бібліографічний опис  Verylargescale integration device for parallel vertical group computing the sum of squared differences / Ivan Tsmots, Ihor. Ihnatiev, Stepan Ivasiev // Scientific Journal of TNTU. — Tern.: TNTU, 2023. — Vol 110. — No 2. — P. 5–14. 
Bibliographic description:  Tsmots I., Ihnatiev I., Ivasiev S. (2023) Verylargescale integration device for parallel vertical group computing the sum of squared differences. Scientific Journal of TNTU (Tern.), vol 110, no 2, pp. 5–14. 
УДК 
681.3 
Ключові слова 
sum of squared differences, device, real time, parallel vertical group method, data flow rate, VLSI device, algorithms. 

Is a paper that proposes a new method for computing sumofsquares differences in a parallel vertical environment. The method is based on a group approach, which allows you to divide the task into several subtasks and calculate them in parallel. The article considers the problem of calculating the sum of squared differences between elements of large data arrays. Applying traditional methods of calculating such sums in parallel environments can be inefficient due to the exchange of large amounts of data between nodes. The proposed method allows to reduce the amount of transmitted data and increase the efficiency of calculations. The article proposes a new method for calculating the sum of squared differences, which allows to increase the efficiency of calculations in a parallel vertical environment. Testing of the method on different data sets shows its high efficiency compared to traditional methods of calculating sums of squared differences in parallel environments. The proposed method can be applied in various areas that require the processing of large volumes of data, and allows to increase the efficiency of calculations and reduce their execution time. The methods, algorithms and structures of devices for computing the sum of squared differences have been analyzed and their defects have been defined in the article. It has been defined that the device for computing the sum of squared differences should support the next: high device utilization; the use of capabilities and benefits of VLSI; shortterm development and moderate price. The development of the device has been suggested by computing the sum of squared differences using modularity principles, coordination between data flow and computing capability of the device, pipelining and space parallelism, localization and simplification of links with elements. The proposed method can be useful for researchers in the fields of parallel computing and data processing, and can find applications in various fields such as data science, machine learning, image processing, and bioinformatics. 
ISSN:  25224433 
Перелік літератури 

Tsmots I., Rabyk V., Skorokhoda O., Teslyuk T. Neural element of parallelstream type with preliminary formation of group partial products. Electronics and information technologies (ELIT2019) : proceedings of the XIth International scientific and practical conference, 16 –18 September, 2019, Lviv, Ukraine. 2019. P. 154–158.

Tsmots I. H., Lukashchuk Yu. A., Khavalko V. M., Rabyk V. H. Modeli neiropodibnoho elementa paralelnoparalelnoho typu. Modeliuvannia ta informatsiini tekhnolohii. 2019. Vyp. 86. P. 119–126/

Tsmots I., Teslyuk V., Teslyuk T., Ihnatyev I. Basic Components of Neuronetworks with Parallel Vertical Group Data RealTime Processing. Advances in Intelligent Systems and Computing II, Advances in Intelligent Systems and Computing 689. Springer International Publishing AG 2018. P. 558–576.

Wu R, Guo X, Du J, Li J (2021) Accelerating neural network inference on FPGAbased platforms – A survey. Electronics 10:1025. URL: https:// doi. org/ 10. 3390/ elect ronic s1009 1025.

Sze M., Chen S., Yang Y. and Huang T. S. “Efficient Processing of Deep Neural Networks: A Tutorial and Survey,” Proceedings of the IEEE. Vol. 105. No. 12. P. 2295–2329, Dec. 2017.

Chen T., Du Z., Sun N., Wang J., Wu C., Chen Y. and Temam O. “DianNao: A SmallFootprint HighThroughput Accelerator for Ubiquitous MachineLearning,” Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). P. 269–284, Mar. 2014.

Zhang Y., Chen T., Du S. S. and Wang J. “Maximizing CNN Accelerator Efficiency through Resource Partitioning and Pipeline Parallelism,” Proceedings of the 2016 ACM SIGARCH International Conference on Computer Architecture (ISCA). P. 573–586, Jun. 2016.

D. H. D. Zhou, Y. Zhang, Z. Zhou, and J. Cong, “FPGABased Deep Learning Accelerator with Stacked Sparse Autoencoder,” Proceedings of the 2016 ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays (FPGA). P. 26–35, Feb. 2016.

Yuan Wang, ChenYi Lee, and TsiChung Chen. “Parallel Implementation of SumofSquaresofDifferences for Image Matching.” IEEE Transactions on Circuits and Systems for Video Technology. Vol. 26. No. 9. 2016. P. 1711–1721.

Rajib Dey, Sushmita Roy, and Somnath Paul. “Efficient Hardware Implementation of Sum of Absolute Difference and Sum of Squared Difference for Real Time Video Processing.” 2018 International Conference on Signal Processing and Communications (SPCOM), 2018, p. 1–5.

D. V. Le, D. T. Anh, T. Q. Anh, and N. T. Thanh. “A Novel Fast and Low Power Sum of Squared Differences Architecture for Motion Estimation in Video Coding.” 2017 7th International Conference on Communications and Electronics (ICCE), 2017, p. 11–16.

F. B. Shams, S. A. Samad, and S. A. Samad. “FPGA Based Parallel Architecture for Sum of Absolute Differences and Sum of Squared Differences Using Novel Pipelining.” 2017 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2017, p. 63–68.

TrungKien Le, ThanhTung Do, VanAnh Nguyen, ThanhBinh Nguyen, and DucMinh Pham. “Design and Implementation of High Performance Sum of Absolute Differences and Sum of Squared Differences Circuits for Video Coding.” 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, p. 226–229.

Jiaqi Yan, Zhaohui Yang, Shuai Zhang, Qingyu Hou, and Junzhao Du. “A Novel Algorithm and VLSI Architecture for SumofSquaresofDifferences in Image Matching.” Journal of Signal Processing Systems. Vol. 89. No. 3. 2017. P. 465–478.

YiFan Lin and ChenYi Lee. “A LowPower Parallel Processing Architecture for SumofSquaredDifferencesBased Image Matching.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 26. No. 10. 2018. P. 1925–1937.

Xinyu Liu, Jianpeng Xue, Hailiang Zhang, and Xiande Huang. “An Efficient Reconfigurable Hardware Architecture for Sum of Squared Differences Algorithm.” 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018, p. 1–6.

M. Emre Celebi and Yasemin Yardimci. “A Hardware Design of Sum of Squared Differences and Its Application on Stereo Matching.” 2018 26th Signal Processing and Communications Applications Conference (SIU), 2018, p. 1–4.

Tsmots I., Teslyuk V., Kryvinska N., Skorokhoda O., Kazymyra I. Development of a generalized model for parallelstreaming neural element and structures for scalar product calculation devices. Journal of Supercomputing. 2022.

References: 

Tsmots I., Rabyk V., Skorokhoda O., Teslyuk T. Neural element of parallelstream type with preliminary formation of group partial products. Electronics and information technologies (ELIT2019) : proceedings of the XIth International scientific and practical conference, 16 –18 September, 2019, Lviv, Ukraine. 2019. P. 154–158.

Tsmots I. H., Lukashchuk Yu. A., Khavalko V. M., Rabyk V. H. Modeli neiropodibnoho elementa paralelnoparalelnoho typu. Modeliuvannia ta informatsiini tekhnolohii. 2019. Vyp. 86. P. 119–126/

Tsmots I., Teslyuk V., Teslyuk T., Ihnatyev I. Basic Components of Neuronetworks with Parallel Vertical Group Data RealTime Processing. Advances in Intelligent Systems and Computing II, Advances in Intelligent Systems and Computing 689. Springer International Publishing AG 2018. P. 558–576.

Wu R, Guo X, Du J, Li J (2021) Accelerating neural network inference on FPGAbased platforms – A survey. Electronics 10:1025. URL: https:// doi. org/ 10. 3390/ elect ronic s1009 1025.

Sze M., Chen S., Yang Y. and Huang T. S. “Efficient Processing of Deep Neural Networks: A Tutorial and Survey,” Proceedings of the IEEE. Vol. 105. No. 12. P. 2295–2329, Dec. 2017.

Chen T., Du Z., Sun N., Wang J., Wu C., Chen Y. and Temam O. “DianNao: A SmallFootprint HighThroughput Accelerator for Ubiquitous MachineLearning,” Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). P. 269–284, Mar. 2014.

Zhang Y., Chen T., Du S. S. and Wang J. “Maximizing CNN Accelerator Efficiency through Resource Partitioning and Pipeline Parallelism,” Proceedings of the 2016 ACM SIGARCH International Conference on Computer Architecture (ISCA). P. 573–586, Jun. 2016.

D. H. D. Zhou, Y. Zhang, Z. Zhou, and J. Cong, “FPGABased Deep Learning Accelerator with Stacked Sparse Autoencoder,” Proceedings of the 2016 ACM/SIGDA International Symposium on FieldProgrammable Gate Arrays (FPGA). P. 26–35, Feb. 2016.

Yuan Wang, ChenYi Lee, and TsiChung Chen. “Parallel Implementation of SumofSquaresofDifferences for Image Matching.” IEEE Transactions on Circuits and Systems for Video Technology. Vol. 26. No. 9. 2016. P. 1711–1721.

Rajib Dey, Sushmita Roy, and Somnath Paul. “Efficient Hardware Implementation of Sum of Absolute Difference and Sum of Squared Difference for Real Time Video Processing.” 2018 International Conference on Signal Processing and Communications (SPCOM), 2018, p. 1–5.

D. V. Le, D. T. Anh, T. Q. Anh, and N. T. Thanh. “A Novel Fast and Low Power Sum of Squared Differences Architecture for Motion Estimation in Video Coding.” 2017 7th International Conference on Communications and Electronics (ICCE), 2017, p. 11–16.

F. B. Shams, S. A. Samad, and S. A. Samad. “FPGA Based Parallel Architecture for Sum of Absolute Differences and Sum of Squared Differences Using Novel Pipelining.” 2017 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2017, p. 63–68.

TrungKien Le, ThanhTung Do, VanAnh Nguyen, ThanhBinh Nguyen, and DucMinh Pham. “Design and Implementation of High Performance Sum of Absolute Differences and Sum of Squared Differences Circuits for Video Coding.” 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, p. 226–229.

Jiaqi Yan, Zhaohui Yang, Shuai Zhang, Qingyu Hou, and Junzhao Du. “A Novel Algorithm and VLSI Architecture for SumofSquaresofDifferences in Image Matching.” Journal of Signal Processing Systems. Vol. 89. No. 3. 2017. P. 465–478.

YiFan Lin and ChenYi Lee. “A LowPower Parallel Processing Architecture for SumofSquaredDifferencesBased Image Matching.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 26. No. 10. 2018. P. 1925–1937.

Xinyu Liu, Jianpeng Xue, Hailiang Zhang, and Xiande Huang. “An Efficient Reconfigurable Hardware Architecture for Sum of Squared Differences Algorithm.” 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018, p. 1–6.

M. Emre Celebi and Yasemin Yardimci. “A Hardware Design of Sum of Squared Differences and Its Application on Stereo Matching.” 2018 26th Signal Processing and Communications Applications Conference (SIU), 2018, p. 1–4.

Tsmots I., Teslyuk V., Kryvinska N., Skorokhoda O., Kazymyra I. Development of a generalized model for parallelstreaming neural element and structures for scalar product calculation devices. Journal of Supercomputing. 2022.

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